The present invention relates to a semiconductor storage apparatus and in particular to a semiconductor storage apparatus which is suitable for a high-speed operation.
Dynamic random access memory (DRAM) has been required to operate faster in recent years. In particular, DRAM has been required to speed up a data write operation, which takes more time than a data read operation or refresh operation. Means for meeting such a requirement are disclosed in Japanese Unexamined Patent Application Publication Nos. 2003-16783 and 10-162577.
A semiconductor storage apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2003-16783 includes a memory cell array having multiple pairs of bit lines BLt/BLc disposed therein, sense amplifiers corresponding to the pairs of bit lines BLt/BLc, column gates corresponding to the pairs of bit lines BLt/BLc and configured to select a column of the memory cell array, and a write buffer circuit configured to hold data to be written to a memory cell. This semiconductor storage apparatus selects a column when the sense amplifiers are inactivated; it writes data to a pair of bit lines BLt/BLc belonging to the selected column when the sense amplifiers are inactivated.
A semiconductor storage apparatus disclosed in Japanese Unexamined Patent Application Publication No. 10-162577 includes a row decoder configured to select a row of a memory cell array, a column selection gate configured to select a column of the memory cell array, a column decoder configured to output a column selection signal to the column selection gate, multiple sense amplifiers connected between the memory cell array and the column selection gate and disposed on the columns of the memory cell array one-on-one, and a sense amplifier control circuit for activating the sense amplifiers. This sense amplifier control circuit activates a sense amplifier corresponding to a column selected by the column selection gate independently of the sense amplifiers on the other columns.
Other related technologies are disclosed in the following Patent Literatures.
A semiconductor storage apparatus disclosed in Japanese Unexamined Patent Application Publication No. 8-96578 includes a transfer gate configured to transfer data between a data latch and a sense amplifier, a transfer gate control circuit configured to control the transfer gate, and a sense amplifier control circuit configured to control the operation of the sense amplifier. In writing data, this semiconductor storage apparatus latches the data in the data latch in advance, controls the transfer gate using the transfer gate control circuit to transfer the data from the data latch to a pair of bit lines, and subsequently activates the sense amplifier using the sense amplifier control circuit.
A memory circuit disclosed in Japanese Unexamined Patent Application Publication No. 4-153987 has a function of writing data simultaneously to multiple memory cells on the same word line using one write buffer. This memory circuit includes a sense amplifier drive circuit configured to inactivate a sense amplifier in writing data.
A semiconductor storage apparatus disclosed in Japanese Unexamined Patent Application Publication No. 6-162765 includes a memory array including perpendicularly disposed multiple word lines and bit lines and memory cells disposed at intersections of the word lines and bit lines in a grid, a common data line to which a specified bit line is selectively connected, and a sense amplifier including multiple unit amplifier circuits corresponding to the bit lines. In a write operation, this semiconductor storage apparatus transmits a write signal to a specified bit line via a common data line and subsequently activates a corresponding unit amplifier circuit.
A semiconductor storage apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2000-123574 includes multiple main sense amplifiers, multiple sub-sense amplifier columns, pairs of main bit lines connecting the main sense amplifiers and the sub-sense amplifier columns, and a memory cell array disposed between the sub-sense amplifier columns. In each pair of main bit lines, main bit lines intersect each other multiple times in such a manner to alternately change the positions thereof and protrude by a length of δ from a sub-sense amplifier column which is most distant from the main sense amplifiers. δ=γ−α−β where α is the length of a main bit line in a main sense amplifier; β is the distance between a main sense amplifier and a sub-sense amplifier column closest to the main sense amplifier; and γ is the distance between the sub-sense amplifier columns.